return -ENOSYS;
}
-static int p2m_create_entry(struct domain *d,
+/* Allocate a new page table page and hook it in via the given entry */
+static int p2m_create_table(struct domain *d,
lpae_t *entry)
{
struct p2m_domain *p2m = &d->arch.p2m;
clear_page(p);
unmap_domain_page(p);
- pte = mfn_to_p2m_entry(page_to_mfn(page));
+ pte = mfn_to_p2m_entry(page_to_mfn(page), MATTR_MEM);
write_pte(entry, pte);
int alloc,
paddr_t start_gpaddr,
paddr_t end_gpaddr,
- paddr_t maddr)
+ paddr_t maddr,
+ int mattr)
{
int rc;
struct p2m_domain *p2m = &d->arch.p2m;
{
if ( !first[first_table_offset(addr)].p2m.valid )
{
- rc = p2m_create_entry(d, &first[first_table_offset(addr)]);
+ rc = p2m_create_table(d, &first[first_table_offset(addr)]);
if ( rc < 0 ) {
printk("p2m_populate_ram: L1 failed\n");
goto out;
if ( !second[second_table_offset(addr)].p2m.valid )
{
- rc = p2m_create_entry(d, &second[second_table_offset(addr)]);
+ rc = p2m_create_table(d, &second[second_table_offset(addr)]);
if ( rc < 0 ) {
printk("p2m_populate_ram: L2 failed\n");
goto out;
goto out;
}
- pte = mfn_to_p2m_entry(page_to_mfn(page));
+ pte = mfn_to_p2m_entry(page_to_mfn(page), mattr);
write_pte(&third[third_table_offset(addr)], pte);
} else {
- lpae_t pte = mfn_to_p2m_entry(maddr >> PAGE_SHIFT);
+ lpae_t pte = mfn_to_p2m_entry(maddr >> PAGE_SHIFT, mattr);
write_pte(&third[third_table_offset(addr)], pte);
maddr += PAGE_SIZE;
}
paddr_t start,
paddr_t end)
{
- return create_p2m_entries(d, 1, start, end, 0);
+ return create_p2m_entries(d, 1, start, end, 0, MATTR_MEM);
}
int map_mmio_regions(struct domain *d,
paddr_t end_gaddr,
paddr_t maddr)
{
- return create_p2m_entries(d, 0, start_gaddr, end_gaddr, maddr);
+ return create_p2m_entries(d, 0, start_gaddr, end_gaddr, maddr, MATTR_DEV);
}
int guest_physmap_add_page(struct domain *d,
{
return create_p2m_entries(d, 0, gpfn << PAGE_SHIFT,
(gpfn + (1<<page_order)) << PAGE_SHIFT,
- mfn << PAGE_SHIFT);
+ mfn << PAGE_SHIFT, MATTR_MEM);
}
void guest_physmap_remove_page(struct domain *d,
#define MAIR0VAL 0xeeaa4400
#define MAIR1VAL 0xff000004
+/*
+ * Attribute Indexes.
+ *
+ * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
+ * table entry. They are indexes into the bytes of the MAIR*
+ * registers, as defined above.
+ *
+ */
#define UNCACHED 0x0
#define BUFFERABLE 0x1
#define WRITETHROUGH 0x2
#define DEV_WC BUFFERABLE
#define DEV_CACHED WRITEBACK
+/*
+ * Stage 2 Memory Type.
+ *
+ * These are valid in the MemAttr[3:0] field of an LPAE stage 2 page
+ * table entry.
+ *
+ */
+#define MATTR_DEV 0x1
+#define MATTR_MEM 0xf
#ifndef __ASSEMBLY__
return e;
}
-static inline lpae_t mfn_to_p2m_entry(unsigned long mfn)
+static inline lpae_t mfn_to_p2m_entry(unsigned long mfn, unsigned int mattr)
{
paddr_t pa = ((paddr_t) mfn) << PAGE_SHIFT;
lpae_t e = (lpae_t) {
.p2m.sh = LPAE_SH_OUTER,
.p2m.write = 1,
.p2m.read = 1,
- .p2m.mattr = 0xf,
+ .p2m.mattr = mattr,
.p2m.table = 1,
.p2m.valid = 1,
};